/**************************************
@ filename    : uart_test_env.vh
@ author      : yyrwkk
@ create time : 2025/04/17 23:46:06
@ version     : v1.0.0
**************************************/
`ifndef UART_TEST_ENV__VH
`define UART_TEST_ENV__VH

`define FPGA_SOURCE

`define UART_BAUD_DIV        (1000 ) // baudrate div value : f_clk / baudrate
`define UART_TARGET_BITS     (3'h7 ) // data bits length-1 : 4,5,6,7
`define UART_PARITY_EN       (1'b0 ) // parity enable
`define UART_PARITY_SEL      (2'b00) // parity select : 00->odd, 01->even, 10-> constant 0, 11: constant 1
`define UART_STOP_BITS       (1'b1 ) // 0->1bit stop bits, 1-> 2bit stop bits

`define FIFO_ADDR_WIDTH      (1    )

`endif
